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| 200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP) This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 400 mil TSOP II packages on a 200pin glass-epoxy substrate. This Hynix 256Mb D ver. based unbuffered SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES * * * * * * * JEDEC Standard 200-pin small outline, dual in-line memory module (SO-DIMM) Two ranks 32M x 64 and One rank 32M x 64, 16M x 64 organization 2.6V 0.1V VDD and VDDQ Power supply for DDR400, 2.5V 0.2V for DDR333 and below All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 133/166/200MHz DLL aligns DQ and DQS transition with CK transition Programmable CAS Latency: DDR266(2, 2.5 clock), DDR333(2.5 clock), DDR400(3 clock) * * * * * * * Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Edge-aligned DQS with data outs and Center-aligned DQS with data inputs Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial Presence Detect (SPD) with EEPROM Built with 256Mb DDR SDRAMs in 400 mil TSOP II packages Lead-free product listed for each configuration (RoHS compliant) ADDRESS TABLE Organization 256MB 256MB 128MB 32M x 64 32M x 64 16M x 64 Ranks 2 1 1 SDRAMs 16Mb x 16 32Mb x 8 16Mb x 16 # of DRAMs 8 8 4 # of row/bank/column Address 13(A0~A12)/2(BA0,BA1)/9(A0~A8) 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 13(A0~A12)/2(BA0,BA1)/9(A0~A8) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms PERFORMANCE RANGE Part-Number Suffix Speed Bin CL - tRCD- tRP CL=3 Max Clock Frequency CL=2.5 CL=2 -D431 DDR400B 3-3-3 200 166 133 -J DDR333 2.5-3-3 166 133 -K DDR266A 2-3-3 133 133 -H DDR266B 2.5-3-3 133 133 Unit CK MHz MHz MHz Note: 1. 2.6V +/- 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V +/- 0.2V for DDR333 and below Rev. 1.1 / May. 2005 1 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 11 200pin Unbuffered DDR SDRAM SO-DIMMs ORDERING INFORMATION Part Number HYMD216M646D[L]6-D43/J/K/H HYMD216M646D[L]P6-D43/J/K/H HYMD232M646D[L]8-D43/J/K/H HYMD232M646D[L]P8-D43/J/K/H HYMD232M646D[L]6-D43/J/K/H HYMD232M646D[L]P6-D43/J/K/H Density 128MB 128MB 256MB 256MB 256MB 256MB Organization Ranks 16M x 64 16M x 64 32M x 64 32M x 64 32M x 64 32M x 64 1 1 1 1 2 2 # of DRAMs 4 4 8 8 8 8 Material Normal Lead-free1 Normal Lead-free1 Normal Lead-free1 DIMM Dimension 67.60 x 31.75 x 3.8 [mm3] Note: 1. The "Pb-free" products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability. * These products are built with HY5DU564(8,16)22DT[L][P] the Hynix DDR SDRAM component. Rev. 1.1 / May. 2005 2 11 200pin Unbuffered DDR SDRAM SO-DIMMs PIN DESCRIPTION Pin CK0~2, /CK0~2 /CS0, /CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A13 A10/AP BA0, BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS8 DM0~8 Pin Description Differential Clock Inputs Chip Select Inputs Clock Enable Inputs Commend Sets Inputs Address Inputs Address Input/Autoprecharge Bank Address Data Inputs/Outputs Data Check bits Data Strobes Data-in Masks Pin VDD VSS VREF VDDSPD VDDID SA0~SA2 SCL SDA DU NC TEST Pin Description Power Supply for Core and I/O Ground Input/Output Reference Power Supply for SPD VDD, VDDQ Level Detection SPD Address Inputs SPD Clock Input SPD Data Input/Output Do not Use No Connection Reserved for test equipment use PIN ASSIGNMENT Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 /CK2 VDD CKE1 DU A12 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU VSS VSS VDD VDD CKE0 DU A11 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Name A9 VSS A7 A5 A3 A1 VDD A10,AP BA0 /WE /CS0 NC,A13 VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Name A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS Pin 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Name DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Name DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC,TEST note: 1. Pins 71, 72, 73, 74,77,78,79, 80, 83, 84 are reserved for x72 variants of this module and are not used on the x64 versions. 2. Pin 86 is reserved for a registered variant of this module and is not used on the unbuffered version. 3. Pin 89, 91 are reserved for x72 modules or registered modules and is not used on the unbuffered version. 4. Pin 95, 122 are not used for single rank module. 5. Pin 123 is "NC" for 256MB, 512MB, and 1GB, or "A13" for 2GB module. Rev. 1.1 / May. 2005 3 11 200pin Unbuffered DDR SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 128MB, 16M x 64 Unbuffered SO-DIMM: HYMD216M646D[L][P]6 /CS DQS0 DM0 DQ00 DQ01 DQ02 DQ03 DQ04 DQ05 DQ06 DQ07 DQS1 DM1 DQ08 DQ09 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS /CS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM D0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS /CS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM D2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 LDQS LDM /S LDQS LDM /S I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM D1 D3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 # Unless otherwise noted, resistor values are 22O +- 5% BA0-BA1 A0-AN /RAS /CAS /WE SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 Serial Presence Detector (SPD) CK0 /CK0 CK1 /CK1 CK2 /CK2 2 loads SCL SA0 SA1 SA2 A0 A1 A2 2 loads 0 loads SDA WP CKE0 CKE1 VDD SPD VREF VDD VSS VDDID SDRAMs D0-D3 N.C. SPD SDRAMS DO-D7 SDRAMS DO-D7 VDD and VDDQ SDRAMS DO-D7,SPD Strap:see Note 4 Notes : DQ wiring may differ from that described in this drawing : however DQ/DM/DQS relationship are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open) : VDD = VDDQ Strap in (closed) : VDD VDDQ Rev. 1.1 / May. 2005 4 11 200pin Unbuffered DDR SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]8 /CS DQS0 DM0 DQ00 DQ01 DQ02 DQ03 DQ04 DQ05 DQ06 DQ07 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /CS D0 DQS1 DM1 DQ08 DQ09 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /CS D1 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /CS D4 /CS D5 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /CS D2 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /CS D3 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /CS D6 /CS D7 # Unless otherwise noted, resistor values are 22O +- 5% BA0-BA1 A0-AN /RAS /CAS SDRAMs D0-D7 SDRAMs D0-D7 SDRAMs D0-D7 SDRAMs D0-D7 SCL Serial Presence Detector (SPD) CK0 /CK0 4 loads SA0 SA1 SA2 A0 A1 A2 WP /WE CKE0 CKE1 SDRAMs D0-D7 SDRAMs D0-D3 N.C. SDA CK1 /CK1 CK2 /CK2 4 loads 0 loads VDD SPD VREF VDD VSS VDDID SPD SDRAMS DO-D7 SDRAMS DO-D7 VDD and VDDQ SDRAMS DO-D7,SPD Strap:see Note 4 Notes : DQ wiring may differ from that described in this drawing : however DQ/DM/DQS relationship are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open) : VDD = VDDQ Strap in (closed) : VDD VDDQ Rev. 1.1 / May. 2005 5 11 200pin Unbuffered DDR SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]6 /CS1 /CS0 DQS0 DM0 DQ00 DQ01 DQ02 DQ03 DQ04 DQ05 DQ06 DQ07 DQS1 DM1 DQ08 DQ09 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM D0 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM D2 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 LDQS /CS LDM LDQS /CS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM D1 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D5 D3 I/O7 UDQS UDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 D7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 # Unless otherwise noted, resistor values are 22O +- 5% BA0-BA1 A0-AN /RAS /CAS /WE SDRAMs D0-D7 SDRAMs D0-D7 SDRAMs D0-D7 SDRAMs D0-D7 SDRAMs D0-D7 Serial Presence Detector (SPD) CK0 /CK0 CK1 /CK1 CK2 /CK2 4 loads SCL SA0 SA1 SA2 A0 A1 A2 4 loads 0 loads SDA WP CKE0 CKE1 VDD SPD VREF VDD VSS VDDID SDRAMs D0-D3 SDRAMs D4-D7 SPD SDRAMS DO-D7 SDRAMS DO-D7 VDD and VDDQ SDRAMS DO-D7,SPD Strap:see Note 4 Notes : DQ wiring may differ from that described in this drawing : however DQ/DM/DQS relationship are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open) : VDD = VDDQ Strap in (closed) : VDD VDDQ Rev. 1.1 / May. 2005 6 11 200pin Unbuffered DDR SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS1 Parameter Operating Temperature (Ambient) Storage Temperature Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Voltage on inputs relative to Vss Voltage on I/O pins relative to Vss Output Short Circuit Current Soldering Temperature Time Symbol TA TSTG VDD VDDQ VINPUT VIO IOS TSOLDER Rating 0 ~ 70 -55 ~ 150 -1.0 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -0.5 ~3.6 50 260 10 oC Unit oC oC V V V V mA Sec Note: 1. Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Power Supply Voltage (DDR 200, 266, 333) Power Supply Voltage (DDR 400) Power Supply Voltage (DDR 200, 266, 333) Power Supply Voltage (DDR 400) Input High Voltage Input Low Voltage Termination Voltage Reference Voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input Leakage Current Output Leakage Current Output High Current Normal Strength (min VDDQ, min VREF, min VTT) Output Driver (VOUT=VTT 0.84) Output Low Current (min VDDQ, max VREF, max VTT) Half Strength Out- Output High Current put Driver (min VDDQ, min VREF, min VTT) (VOUT=VTT 0.68) Output Low Current Symbol VDD VDD VDDQ VDDQ VIH VIL VTT VREF VIN(DC) VID(DC) VI(RATIO) ILI ILO IOH IOL IOH IOL Min 2.3 2.5 2.3 2.5 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ -0.3 0.36 0.71 -2 -5 -16.8 16.8 -13.6 13.6 Typ. 2.5 2.6 2.5 2.6 VREF 0.5*VDDQ - Max 2.7 2.7 2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ VDDQ+0.3 VDDQ+0.6 1.4 2 5 - Unit V V V V V V V V V V uA uA mA mA mA mA Note 2 1 1,2 3 4 5 6 7 8 (min VDDQ, max VREF, max VTT) Note: 1. VDDQ must not exceed the level of VDD. 2. For DDR400, VDD=2.6V 0.1V, VDDQ=2.6V 0.1V 3. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value. 5. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 6. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 7. VIN=0 to VDD, All other pins are not tested under VIN =0V. 8. DQs are disabled, VOUT=0 to VDDQ. Rev. 1.1 / May. 2005 7 11 200pin Unbuffered DDR SDRAM SO-DIMMs IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) 128MB, 32M x 64 Unbuffered SO-DIMM: HYMD216M646D[L][P]6 Symbol Test Condition One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE=<0.2V; External clock on; tCK Normal =tCK(min) Low Power Four bank interleaving with BL=4 Refer to the following page for detailed test condition Speed -D43 360 -J 320 -K 280 -H 280 Unit Note IDD0 mA IDD1 IDD2P IDD2F IDD3P 400 40 240 60 400 40 200 60 360 40 160 60 360 40 160 60 mA mA mA mA IDD3N 160 140 120 120 mA IDD4R 800 760 680 680 mA IDD4W 800 760 680 680 mA IDD5 IDD6 IDD7 600 12 6 1000 560 520 520 mA mA mA mA 12 6 960 12 6 880 12 6 880 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 / May. 2005 8 11 200pin Unbuffered DDR SDRAM SO-DIMMs IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) 256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]8 Symbol Test Condition One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE=<0.2V; External clock on; tCK Normal =tCK(min) Low Power Four bank interleaving with BL=4 Refer to the following page for detailed test condition Speed -D43 720 -J 640 -K 560 -H 560 Unit Note IDD0 mA IDD1 IDD2P IDD2F IDD3P 800 80 480 120 800 80 400 120 720 80 320 120 720 80 320 120 mA mA mA mA IDD3N 400 360 320 320 mA IDD4R 1440 1280 1200 1200 mA IDD4W 1440 1280 1200 1200 mA IDD5 IDD6 IDD7 1200 24 12 1840 1200 1120 1120 mA mA mA mA 24 12 1760 24 12 1600 24 12 1600 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 / May. 2005 9 11 200pin Unbuffered DDR SDRAM SO-DIMMs IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) 256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]6 Symbol Test Condition One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE=<0.2V; External clock on; tCK Normal =tCK(min) Low Power Four bank interleaving with BL=4 Refer to the following page for detailed test condition Speed DDR400B DDR333 DDR266A DDR266B 600 520 440 440 Unit Note IDD0 mA IDD1 IDD2P IDD2F IDD3P 640 80 480 120 600 80 400 120 520 80 320 120 520 80 320 120 mA mA mA mA IDD3N 440 380 320 320 mA IDD4R 1040 960 840 840 mA IDD4W 1040 960 840 840 mA IDD5 IDD6 IDD7 840 24 12 1240 800 720 720 mA mA mA mA 24 12 1160 24 12 1040 24 12 1040 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 10 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.31 0.7 0.5*VDDQ-0.2 Max VREF - 0.31 VDDQ + 0.6 0.5*VDDQ+0.2 Unit V V V V 1 2 Note Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF OUTPUT LOAD CIRCUIT VTT RT=50 Output Zo=50 VREF CL=30pF Rev. 11 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs CAPACITANCE (TA=25oC, f=100MHz) 128MB: HYMD216M646D[L][P]6 Input/Output Pins A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0, CKE1 /CS0, /CS1 CK0, /CK0, CK1, /CK1, CK2, /CK2 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CI01 Min 28 28 28 28 16 7 7 Max 40 40 40 40 25 12 12 Unit pF pF pF pF pF pF pF 256MB: HYMD232M646D[L][P]8 Input/Output Pins A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0 /CS CK0, /CK0, CK1, /CK1, CK2, /CK2 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CI01 Min 36 36 36 36 18 7 7 Max 48 48 40 40 27 12 12 Unit pF pF pF pF pF pF pF 256MB: HYMD232M646D[L][P]6 Input/Output Pins A0 ~ A12, BA0, BA1 /RAS, /CAS, /WE CKE0, CKE1 /CS0, /CS1 CK0, /CK0, CK1, /CK1, CK2, /CK2 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CI01 Min 36 36 28 28 18 12 12 Max 48 48 40 40 27 18 18 Unit pF pF pF pF pF pF pF Rev. 12 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted) Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Internal Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time22 CL = 3 System Clock Cycle CL = 2.5 Time24 CL = 2 Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR DDR400B Min 55 70 40 tRCD or tRASmin 15 10 1 15 15 2 (tWR/ tCK) + (tRP/tCK) 5 tCK tCH tCL tAC 0.45 0.45 -0.7 -0.55 tHP -tQHS min (tCL,tCH) Max 70K DDR333 Min 60 72 42 tRCD or tRASmin 18 12 1 18 15 1 (tWR/ tCK) + (tRP/tCK) 6 7.5 0.45 0.45 -0.7 -0.6 tHP -tQHS min (tCL,tCH) Max 70K DDR266A Min 65 75 45 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK) + (tRP/tCK) 7.5 7.5 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) Max 120K DDR266B Min 65 75 45 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK) + (tRP/tCK) 7.5 10 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) Max 120K DDR200 Min 70 80 50 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK) + (tRP/tCK) 8.0 10 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) Max 120K UNIT ns ns ns ns ns ns tCK ns ns tCK tDAL - - - - - tCK 10 0.55 0.55 0.7 0.55 0.4 0.5 12 12 0.55 0.55 0.7 0.6 0.45 0.55 12 12 0.55 0.55 0.75 0.75 0.5 0.75 12 12 0.55 0.55 0.75 0.75 0.5 0.75 12 12 0.55 0.55 0.75 0.75 0.6 0.75 ns ns tCK tCK ns ns ns ns ns ns ns DQS-Out edge to Clock tDQSCK edge Skew DQS-Out edge to DataOut edge Skew21 Data-Out hold time from DQS20 Clock Half Period19,20 Data Hold Skew Factor20 Valid Data Output Window tDQSQ tQH tHP tQHS tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ Rev. 13 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs - Continue Parameter Data-out high-impedance window from CK,/CK10 Data-out low-impedance window from CK, /CK10 Input Setup Time (fast slew rate)14,16-18 Input Hold Time (fast slew rate)14,16-18 Input Setup Time (slow slew rate)15-18 Input Hold Time (slow slew rate)15-18 Input Pulse Width17 Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQSIn DQS falling edge to CK setup time DQS falling edge hold time from CK DQ & DM input setup time25 DQ & DM input hold time25 DQ & DM Input Pulse Width17 Read DQS Preamble Time Read DQS Postamble Time Symbol DDR400B Min -0.7 -0.7 0.6 0.6 0.7 0.7 2.2 0.35 0.35 0.72 0.2 0.2 0.4 0.4 1.75 0.9 0.4 0 Max 0.7 0.7 1.25 1.1 0.6 0.6 7.8 DDR333 Min -0.7 -0.7 0.75 0.75 0.8 0.8 2.2 0.35 0.35 0.75 0.2 0.2 0.45 0.45 1.75 0.9 0.4 0 0.25 0.4 2 75 200 Max 0.7 0.7 1.25 1.1 0.6 0.6 7.8 DDR266A Min -0.75 -0.75 0.9 0.9 1.0 1.0 2.2 0.35 0.35 0.75 0.2 0.2 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 75 200 Max 0.75 0.75 1.25 1.1 0.6 0.6 7.8 DDR266B Min -0.75 -0.75 0.9 0.9 1.0 1.0 2.2 0.35 0.35 0.75 0.2 0.2 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 75 200 Max 0.75 0.75 1.25 1.1 0.6 0.6 7.8 DDR200 Min -0.8 -0.8 1.1 1.1 1.1 1.1 2.5 0.35 0.35 0.75 0.2 0.2 0.6 0.6 2 0.9 0.4 0 0.25 0.4 2 80 200 Max 0.8 0.8 1.25 1.1 0.6 0.6 7.8 UNIT tHZ tLZ tIS tIH tIS tIH tIPW tDQSH tDQSL tDQSS tDSS tDSH tDS tDH tDIPW tRPRE tRPST ns ns ns ns ns ns ns tCK tCK tCK tCK tCK ns ns ns tCK tCK ns tCK tCK tCK ns tCK us Write DQS Preamble Setup Time12 tWPRES Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to non-Read command23 Exit Self Refresh to Read command Average Periodic Refresh Interval13,25 11 tWPREH 0.25 tWPST tMRD tXSNR tXSRD tREFI 0.4 2 75 200 - Rev. 14 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs Note: 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Output (VOUT) 30 pF Figure: Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is recognized as LOW. 7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference level for signals other than CK, /CK is VREF. 8. The output timing reference voltage level is VTT. 9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 14. For command/address input slew rate 1.0 V/ns. 15. For command/address input slew rate 0.5 V/ns and 1.0 V/ns 16. For CK & /CK slew rate 1.0 V/ns (single-ended) 17. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 18. Slew Rate is measured between VOH(ac) and VOL(ac). 19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. Rev. 15 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs 20.tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 22. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5 ns tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks = ((2) + (3)) clocks = 5 clocks 23. In all circumstances, tXSNR can be satisfied using tXSNR = tRFCmin + 1*tCK 24. The only time that the clock frequency is allowed to change is during self-refresh mode. 25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. Rev. 16 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performannce. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for DQ/DM/DQS AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) Symbol DCSLEW min 0.5 (Table a.) DDR333 min 0.5 max 4.0 DDR266 min 0.5 max 4.0 DDR200 min 0.5 max 4.0 UNIT Note DDR400 max 4.0 V/ns 1,12 Address & Control Input Setup & Hold Time Derating (Table b.) Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns Delta tIS 0 +50 +100 Delta tIH 0 0 0 UNIT ps ps ps (Table c.) UNIT ps ps ps Note 11 11 11 (Table d.) Note 9 9 9 DQ & DM Input Setup & Hold Time Derating Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns Delta tDS 0 +75 +150 Delta tDH 0 0 0 DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate Input Slew Rate 0.0 ns/V 0.25 ns/V 0.5 ns/V Delta tDS 0 +50 +100 Delta tDH 0 +50 +100 UNIT ps ps ps Note 10 10 10 (Table e.) Note 1,3,4,6,7,8 2,3,4,6,7,8 Output Slew Rate Characteristics (for x4, x8 Devices) Slew Rate Characteristic Pullup Slew Rate Pulldown Slew Rate Typical Range (V/ns) 1.2 - 2.5 1.2 - 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Output Slew Rate Characteristics (for x16 Device) (Table f.) Slew Rate Characteristic Pullup Slew Rate Pulldown Slew Rate Typical Range (V/ns) 1.2 - 2.5 1.2 - 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Note 1,3,4,6,7,8 2,3,4,6,7,8 (Table g.) DDR200 min 0.71 max 1.4 Note 5,12 Output Slew Rate Matching Ratio Characteristics Slew Rate Characteristic Parameter Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR266A min max DDR266B min - max - Rev. 17 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Test Point Output (VOUT) 50 VSSQ Figure: Pullup Slew rate 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ Output (VOUT) 50 Test Point Figure: Pulldown Slew rate 3. Pullup slew rate is measured between (VDDQ/2 - 320 mV 250mV) Pulldown slew rate is measured between (VDDQ/2 + 320mV 250mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example: For typical slew, DQ0 is switching For minimum slew rate, all DQ bits are switching worst case pattern For maximum slew rate, only one DQ is switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. 4. Evaluation conditions Typical: 25 oC (Ambient), VDDQ = nominal, typical process Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process 5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 6. Verified under typical conditions for qualification purposes. 7. TSOP-II package devices only. 8. Only intended for operation up to 256 Mbps per pin. 9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b. The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. 10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c & d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(slew Rate2)} For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100ps. 11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions. 12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. Rev. 18 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit Entry Exit Entry Exit CKEn-1 H H H H H H H H H H L H L H L CKEn X X X X X X X X H L H L H L H /CS L L H L L L L L L L L H L H L H L H L /RAS L L X H L H H L H L L X H X H X H X V X /CAS L L X H H L L H H L L X H X H X H X V /WE L L X H H H L L L H H X H X H X H X V X X X CA CA X RA L H L H H L X X ADDR A10/AP OP code OP code X BA Note 1,2 1,2 1 V V V X V 1 1 1,3 1 1,4 1,5 1 1 1 1 1 1 1 1 1 1 1 1 Precharge Power Down Mode Active Power Down Mode ( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note: 1. DM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Precharge command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. WRITE MASK TRUTH TABLE Function Data Write Data-In Mask Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. CKEn-1 H H CKEn X X /CS, /RAS, /CAS, /WE X X DM L H ADDR A10/AP X X BA Note 1 1 Rev. 19 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs PACKAGE DIMENSIONS 128MB, 16M x 64 Unbuffered SO-DIMM : HYMD216M646D[L][P]6 Front 2.00 mm Component Keepout Area 67.60 mm 2.00 mm Unit: Millimeters Inches 31.75 mm 20.00 mm Side 3.8mm MAX. 1 2.0 mm 2 40 42 39 41 199 Back 200 2.0 mm (Front) 1.1mm MAX. # The location and number of additional device can be different from real product Rev. 21 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs PACKAGE DIMENSIONS 256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]8 Front 2.00 mm Component Keepout Area 67.60 mm 2.00 mm Unit: Millimeters Inches 31.75 mm 20.00 mm 1 39 41 199 2.0 mm 2 40 42 Back 200 Side 2.0 mm 3.8mm MAX. (Front) 1.1mm MAX. Rev. 22 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs PACKAGE DIMENSIONS 256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]6 Front 2.00 mm Component Keepout Area 67.60 mm 2.00 mm Unit: Millimeters Inches 31.75 mm 20.00 mm 1 39 41 199 2.0 mm 2 40 42 Back 200 Side 2.0 mm 3.8mm MAX. (Front) 1.1mm MAX. Rev. 23 1.1 / May. 2005 11 200pin Unbuffered DDR SDRAM SO-DIMMs REVISION HISTORY Revision 1.0 1.1 History First Version Release - Datasheet coverage is changed from an individual module part to a component based module family Corrected PIN DESCRIPTION and PIN ASSIGNMENT Tables Date Feb. 2005 May. 2005 Remark Rev. 24 1.1 / May. 2005 |
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